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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 4717d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 4814d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 4815d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 4818d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 4822d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 4826d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 4826d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 4827d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4827d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4827d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4833d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4835d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4835d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4835d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4848d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4856d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4875d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4875d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4875d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4876d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4876d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4877d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4878d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4879d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4879d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4880d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4881d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4945d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4951d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4952d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v

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