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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 48

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27 added sync simplex FIFO unneback 3806d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 3807d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 3808d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 3809d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 3809d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3810d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3812d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 3875d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 3881d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 3882d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v

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