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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 49

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Rev Log message Author Age Path
49 added WB_B4RAM with byte enable unneback 4095d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4102d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 4198d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 4200d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 4203d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 4207d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 4211d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 4211d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 4211d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4212d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4212d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4218d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4219d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4220d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4220d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4233d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4240d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4260d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4260d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4260d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4261d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4261d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4262d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4263d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4263d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4264d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4265d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4266d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4330d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4336d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v

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