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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 60

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4682d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
59 added WB RAM B3 with byte enable unneback 4683d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
58 corrected EXT unit, rewrite of FF1, FL1 unneback 4700d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
57 corrected EXT unit, rewrite of FF1, FL1 unneback 4700d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
56 WB B4 RAM we fix unneback 4712d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
55 added WB_B4RAM with byte enable unneback 4715d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
54 added WB_B4RAM with byte enable unneback 4715d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
53 added WB_B4RAM with byte enable unneback 4715d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
52 added WB_B4RAM with byte enable unneback 4715d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
51 added WB_B4RAM with byte enable unneback 4715d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
50 added WB_B4RAM with byte enable unneback 4715d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 4715d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4721d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 4817d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 4819d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 4822d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 4826d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 4830d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 4830d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 4830d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4831d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4831d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4837d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4839d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4839d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4839d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4852d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4859d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4879d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4879d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v

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