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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 69

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Rev Log message Author Age Path
69 no arbiter in wb_b3_ram_be unneback 5034d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
68 ram_be updated to optional mem_size unneback 5034d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
67 support up to 8 wbm on arbiter unneback 5035d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
66 RAM_BE ack_o vector unneback 5073d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
65 RAM_BE system verilog version unneback 5073d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
64 SPR reset value unneback 5073d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 5073d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 5073d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 5073d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 5074d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
59 added WB RAM B3 with byte enable unneback 5075d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
58 corrected EXT unit, rewrite of FF1, FL1 unneback 5092d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
57 corrected EXT unit, rewrite of FF1, FL1 unneback 5092d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
56 WB B4 RAM we fix unneback 5104d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
55 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
54 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
53 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
52 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
51 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
50 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 5107d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 5113d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 5210d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 5211d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 5214d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 5218d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 5222d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 5223d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 5223d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 5223d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v

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