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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 80

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Rev Log message Author Age Path
80 avalon read write unneback 3685d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
79 avalon read write unneback 3685d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
78 default to length = 1 unneback 3685d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
77 bridge update unneback 3685d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
76 dependency for wb3 to avalon bus unneback 3685d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
75 added wb to avalon bridge unneback 3685d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
73 no arbiter in wb_b3_ram_be unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
72 no arbiter in wb_b3_ram_be unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
71 no arbiter in wb_b3_ram_be unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
70 no arbiter in wb_b3_ram_be unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
69 no arbiter in wb_b3_ram_be unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
68 ram_be updated to optional mem_size unneback 3693d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
67 support up to 8 wbm on arbiter unneback 3694d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
66 RAM_BE ack_o vector unneback 3732d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
65 RAM_BE system verilog version unneback 3732d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
64 SPR reset value unneback 3732d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3732d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3732d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3732d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3734d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v

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