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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 17

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17 unneback 4499d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4506d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4506d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4506d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4507d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4508d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4509d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4509d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4510d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 4523d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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