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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 21

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 4856d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4857d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4921d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4927d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4927d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4927d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4928d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4929d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4931d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4931d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4931d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 4944d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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