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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 22

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Rev Log message Author Age Path
22 added binary counters unneback 4940d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4941d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4942d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 5006d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 5012d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 5012d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 5013d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 5013d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 5014d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 5016d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 5016d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 5016d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 5029d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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