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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 3932d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 3933d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 3934d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 3935d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 3935d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 3936d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 3937d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4001d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4007d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4007d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4007d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4008d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4009d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4011d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4011d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4011d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 4024d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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