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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 4877d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 4878d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 4879d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4880d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4880d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4881d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4882d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4946d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4952d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4953d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4953d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4953d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4954d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4956d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4956d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4956d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 4969d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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