OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 33

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 5685d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5693d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 5713d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 5713d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 5713d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 5714d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 5714d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 5714d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 5716d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 5716d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 5716d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 5717d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 5719d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 5782d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 5789d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 5789d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 5789d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 5790d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 5790d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 5792d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.