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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 34

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34 added vl_mux2_andor and vl_mux3_andor unneback 3450d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 3463d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3470d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 3490d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 3490d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 3490d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 3491d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 3491d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 3492d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 3493d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 3494d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 3494d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 3495d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 3496d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 3560d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 3566d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 3566d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 3566d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 3567d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 3568d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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