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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 34

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34 added vl_mux2_andor and vl_mux3_andor unneback 4985d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4998d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5005d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 5025d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 5025d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 5025d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 5026d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 5026d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 5027d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 5028d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 5029d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 5029d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 5030d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 5031d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 5095d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 5101d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 5102d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 5102d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 5102d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 5103d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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