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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 34

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34 added vl_mux2_andor and vl_mux3_andor unneback 3237d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 3250d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3258d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 3277d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 3277d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 3277d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 3278d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 3278d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 3279d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 3280d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 3281d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 3281d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 3282d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 3284d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 3347d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 3353d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 3354d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 3354d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 3355d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 3355d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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