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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 36

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36 added generic andor_mux unneback 3802d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3802d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3802d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 3815d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3823d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 3843d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 3843d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 3843d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 3844d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 3844d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 3844d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 3846d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 3846d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 3846d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 3847d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 3849d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 3912d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 3919d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 3919d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 3919d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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