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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 42

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42 updated mux_andor unneback 5219d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 5219d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 5220d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 5220d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 5226d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 5227d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5228d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 5228d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 5241d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5248d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 5268d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 5268d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 5268d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 5269d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 5269d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 5270d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 5271d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 5272d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 5272d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 5273d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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