OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 46

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 4173d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4173d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4173d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4174d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4176d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4239d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4246d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4246d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4246d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4247d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.