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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 50

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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4016d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4016d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4023d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4119d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4120d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4123d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4128d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4132d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4132d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4133d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4133d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4138d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4140d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4140d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4140d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4153d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4161d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 4181d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 4181d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 4181d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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