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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 52

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52 added WB_B4RAM with byte enable unneback 4654d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4654d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4654d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4654d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4661d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4757d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4759d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4762d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4766d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4770d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4770d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4771d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4771d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4777d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4778d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4779d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4779d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4792d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4799d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 4819d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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