URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 70

Rev	Log message	Author	Age	Path
46	updated parity	unneback	4818d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45	updated timing in io models	unneback	4820d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44	added target independet IO functionns	unneback	4823d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43	added logic for parity generation and check	unneback	4827d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42	updated mux_andor	unneback	4831d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40	new build environment with custom.v added as a result file	unneback	4831d 07h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39	added simple port prio based wb arbiter	unneback	4832d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38	updated andor mux	unneback	4832d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37	corrected polynom with length 20	unneback	4838d 00h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36	added generic andor_mux	unneback	4839d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v