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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 90

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64 SPR reset value unneback 3857d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3857d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3857d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3859d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
59 added WB RAM B3 with byte enable unneback 3860d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
56 WB B4 RAM we fix unneback 3889d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
55 added WB_B4RAM with byte enable unneback 3891d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
54 added WB_B4RAM with byte enable unneback 3891d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
53 added WB_B4RAM with byte enable unneback 3891d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 3891d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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