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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 15

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Rev Log message Author Age Path
15 added delay line unneback 3706d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3707d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3707d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3707d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3708d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3710d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3710d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3710d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3723d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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