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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 15

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Rev Log message Author Age Path
15 added delay line unneback 3565d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3565d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3566d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3566d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3567d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3569d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3569d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3569d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3582d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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