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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 18

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Rev Log message Author Age Path
18 naming convention vl_ unneback 4057d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4121d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4127d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4127d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4127d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4128d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4129d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4131d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4131d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4131d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4144d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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