URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 21

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	5030d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18	naming convention vl_	unneback	5031d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17		unneback	5095d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15	added delay line	unneback	5101d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14	reg -> wire for various signals	unneback	5101d 21h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13	cosmetic update	unneback	5101d 23h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12	added wishbone comliant modules	unneback	5102d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11	async fifo simplex	unneback	5103d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10	added dff_ce_clear	unneback	5105d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8	added dff_ce_clear	unneback	5105d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7	mem update	unneback	5105d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6	added library files	unneback	5118d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v