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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 23

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Rev Log message Author Age Path
23 fixed port map error in async fifo 1r1w unneback 4180d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4181d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4181d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4183d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4247d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4253d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4253d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4253d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4254d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4255d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4257d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4257d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4257d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4270d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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