OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 28

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 added sync simplex FIFO unneback 5027d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 5027d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 5028d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 5029d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 5030d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 5030d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 5031d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 5032d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 5096d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 5102d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 5102d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 5102d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 5103d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 5104d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 5106d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 5106d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 5106d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 5119d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.