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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 30

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30 updated counter for level1 and level2 function unneback 3635d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3635d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3636d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3636d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3637d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3638d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3639d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3639d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3640d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3641d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3705d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3711d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3711d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3711d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3712d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3713d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3715d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3715d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3715d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3728d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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