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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 34

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34 added vl_mux2_andor and vl_mux3_andor unneback 3534d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 3547d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3554d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 3574d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 3574d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3574d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3575d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3575d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3576d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3577d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3578d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3578d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3579d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3580d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3644d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3650d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3651d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3651d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3651d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3652d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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