OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 34

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
34 added vl_mux2_andor and vl_mux3_andor unneback 3235d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 3248d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3256d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 3276d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 3276d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3276d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3277d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3277d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3277d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3279d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3279d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3279d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3280d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3282d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3345d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3352d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3352d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3352d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3353d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3353d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.