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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 37

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Rev Log message Author Age Path
37 corrected polynom with length 20 unneback 4848d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4849d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4849d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4849d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 4862d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4870d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 4890d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 4890d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 4890d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4891d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4891d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4891d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4893d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4893d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4894d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4894d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4896d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4959d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4966d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4966d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4966d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4967d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4967d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4969d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4969d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4969d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4982d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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