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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 38

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38 updated andor mux unneback 4381d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4387d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4389d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4389d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4389d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 4402d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4410d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 4429d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 4429d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 4429d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4430d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4430d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4431d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4432d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4433d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4433d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4434d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4435d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4499d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4505d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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