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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 39

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39 added simple port prio based wb arbiter unneback 3825d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 3825d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 3831d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 3832d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3833d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3833d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 3846d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3853d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 3873d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 3873d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3873d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3874d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3874d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3875d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3876d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3876d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3877d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3878d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3879d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3943d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3949d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3949d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3949d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3950d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3951d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3953d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3953d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3953d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3966d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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