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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 52

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30 updated counter for level1 and level2 function unneback 5046d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 5046d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 5047d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 5047d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 5048d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 5049d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 5050d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 5050d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 5051d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 5052d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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