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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 69

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Rev Log message Author Age Path
69 no arbiter in wb_b3_ram_be unneback 4638d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
68 ram_be updated to optional mem_size unneback 4638d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
67 support up to 8 wbm on arbiter unneback 4639d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
66 RAM_BE ack_o vector unneback 4676d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
65 RAM_BE system verilog version unneback 4676d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
64 SPR reset value unneback 4677d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4677d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4677d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4678d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
59 added WB RAM B3 with byte enable unneback 4679d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
56 WB B4 RAM we fix unneback 4708d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
55 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
54 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
53 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 4711d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 4717d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 4814d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4815d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 4818d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4822d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4826d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4827d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4827d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4827d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4833d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4835d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4835d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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