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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 80

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55 added WB_B4RAM with byte enable unneback 4774d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
54 added WB_B4RAM with byte enable unneback 4774d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
53 added WB_B4RAM with byte enable unneback 4774d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52 added WB_B4RAM with byte enable unneback 4774d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 4774d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 4774d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 4774d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 4781d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 4877d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4879d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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