URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 39

Rev	Log message	Author	Age	Path
39	added simple port prio based wb arbiter	unneback	4923d 15h	/versatile_library/trunk/rtl/verilog/wb.v
33	updated wb3wb3_bridge	unneback	4944d 09h	/versatile_library/trunk/rtl/verilog/wb.v
32	added vl_pll for ALTERA (cycloneIII)	unneback	4951d 19h	/versatile_library/trunk/rtl/verilog/wb.v
18	naming convention vl_	unneback	4977d 18h	/versatile_library/trunk/rtl/verilog/wb.v
17		unneback	5041d 07h	/versatile_library/trunk/rtl/verilog/wb.v
14	reg -> wire for various signals	unneback	5047d 20h	/versatile_library/trunk/rtl/verilog/wb.v
13	cosmetic update	unneback	5047d 22h	/versatile_library/trunk/rtl/verilog/wb.v
12	added wishbone comliant modules	unneback	5048d 18h	/versatile_library/trunk/rtl/verilog/wb.v