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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 39

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39 added simple port prio based wb arbiter unneback 3879d 03h /versatile_library/trunk/rtl/verilog/wb.v
33 updated wb3wb3_bridge unneback 3899d 21h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3907d 07h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 3933d 06h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 3996d 19h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 4003d 08h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 4003d 09h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 4004d 05h /versatile_library/trunk/rtl/verilog/wb.v

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