OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 41

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 new build environment with custom.v added as a result file unneback 4845d 06h /versatile_library/trunk/rtl/verilog/wb.v
39 added simple port prio based wb arbiter unneback 4846d 02h /versatile_library/trunk/rtl/verilog/wb.v
33 updated wb3wb3_bridge unneback 4866d 21h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4874d 07h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 4900d 05h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 4963d 19h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 4970d 08h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 4970d 09h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 4971d 05h /versatile_library/trunk/rtl/verilog/wb.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.