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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 52

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52 added WB_B4RAM with byte enable unneback 4054d 05h /versatile_library/trunk/rtl/verilog/wb.v
51 added WB_B4RAM with byte enable unneback 4054d 05h /versatile_library/trunk/rtl/verilog/wb.v
50 added WB_B4RAM with byte enable unneback 4054d 05h /versatile_library/trunk/rtl/verilog/wb.v
49 added WB_B4RAM with byte enable unneback 4054d 06h /versatile_library/trunk/rtl/verilog/wb.v
48 wb updated unneback 4060d 23h /versatile_library/trunk/rtl/verilog/wb.v
44 added target independet IO functionns unneback 4161d 22h /versatile_library/trunk/rtl/verilog/wb.v
42 updated mux_andor unneback 4170d 01h /versatile_library/trunk/rtl/verilog/wb.v
40 new build environment with custom.v added as a result file unneback 4170d 03h /versatile_library/trunk/rtl/verilog/wb.v
39 added simple port prio based wb arbiter unneback 4171d 00h /versatile_library/trunk/rtl/verilog/wb.v
33 updated wb3wb3_bridge unneback 4191d 18h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4199d 04h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 4225d 03h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 4288d 16h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 4295d 05h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 4295d 07h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 4296d 03h /versatile_library/trunk/rtl/verilog/wb.v

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