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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 90

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3973d 19h /versatile_library/trunk/rtl/verilog/wb.v
59 added WB RAM B3 with byte enable unneback 3974d 19h /versatile_library/trunk/rtl/verilog/wb.v
56 WB B4 RAM we fix unneback 4003d 19h /versatile_library/trunk/rtl/verilog/wb.v
55 added WB_B4RAM with byte enable unneback 4006d 01h /versatile_library/trunk/rtl/verilog/wb.v
54 added WB_B4RAM with byte enable unneback 4006d 01h /versatile_library/trunk/rtl/verilog/wb.v
53 added WB_B4RAM with byte enable unneback 4006d 01h /versatile_library/trunk/rtl/verilog/wb.v
52 added WB_B4RAM with byte enable unneback 4006d 01h /versatile_library/trunk/rtl/verilog/wb.v
51 added WB_B4RAM with byte enable unneback 4006d 02h /versatile_library/trunk/rtl/verilog/wb.v
50 added WB_B4RAM with byte enable unneback 4006d 02h /versatile_library/trunk/rtl/verilog/wb.v
49 added WB_B4RAM with byte enable unneback 4006d 02h /versatile_library/trunk/rtl/verilog/wb.v

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