URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl] - Rev 31

Rev	Log message	Author	Age	Path
31	sync FIFO updated	unneback	4895d 23h	/versatile_library/trunk/rtl
30	updated counter for level1 and level2 function	unneback	4895d 23h	/versatile_library/trunk/rtl
29	updated counter for level1 and level2 function	unneback	4895d 23h	/versatile_library/trunk/rtl
28	added sync simplex FIFO	unneback	4897d 00h	/versatile_library/trunk/rtl
27	added sync simplex FIFO	unneback	4897d 00h	/versatile_library/trunk/rtl
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4897d 02h	/versatile_library/trunk/rtl
25	added sync FIFO	unneback	4897d 15h	/versatile_library/trunk/rtl
24	added vl_dff_ce_set	unneback	4898d 23h	/versatile_library/trunk/rtl
23	fixed port map error in async fifo 1r1w	unneback	4899d 14h	/versatile_library/trunk/rtl
22	added binary counters	unneback	4899d 19h	/versatile_library/trunk/rtl
21	reg -> wire in and or mux in logic	unneback	4900d 15h	/versatile_library/trunk/rtl
18	naming convention vl_	unneback	4902d 02h	/versatile_library/trunk/rtl
17		unneback	4965d 15h	/versatile_library/trunk/rtl
15	added delay line	unneback	4971d 23h	/versatile_library/trunk/rtl
14	reg -> wire for various signals	unneback	4972d 04h	/versatile_library/trunk/rtl
13	cosmetic update	unneback	4972d 06h	/versatile_library/trunk/rtl
12	added wishbone comliant modules	unneback	4973d 02h	/versatile_library/trunk/rtl
11	async fifo simplex	unneback	4973d 17h	/versatile_library/trunk/rtl
10	added dff_ce_clear	unneback	4975d 16h	/versatile_library/trunk/rtl
8	added dff_ce_clear	unneback	4975d 16h	/versatile_library/trunk/rtl