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[/] [versatile_library/] [trunk] - Rev 46

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Rev Log message Author Age Path
46 updated parity unneback 4825d 07h /versatile_library/trunk
45 updated timing in io models unneback 4827d 01h /versatile_library/trunk
44 added target independet IO functionns unneback 4830d 01h /versatile_library/trunk
43 added logic for parity generation and check unneback 4834d 05h /versatile_library/trunk
42 updated mux_andor unneback 4838d 04h /versatile_library/trunk
41 typo in registers.v unneback 4838d 06h /versatile_library/trunk
40 new build environment with custom.v added as a result file unneback 4838d 06h /versatile_library/trunk
39 added simple port prio based wb arbiter unneback 4839d 03h /versatile_library/trunk
38 updated andor mux unneback 4839d 03h /versatile_library/trunk
37 corrected polynom with length 20 unneback 4845d 00h /versatile_library/trunk
36 added generic andor_mux unneback 4846d 08h /versatile_library/trunk
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4846d 19h /versatile_library/trunk
34 added vl_mux2_andor and vl_mux3_andor unneback 4846d 19h /versatile_library/trunk
33 updated wb3wb3_bridge unneback 4859d 21h /versatile_library/trunk
32 added vl_pll for ALTERA (cycloneIII) unneback 4867d 07h /versatile_library/trunk
31 sync FIFO updated unneback 4887d 03h /versatile_library/trunk
30 updated counter for level1 and level2 function unneback 4887d 03h /versatile_library/trunk
29 updated counter for level1 and level2 function unneback 4887d 03h /versatile_library/trunk
28 added sync simplex FIFO unneback 4888d 04h /versatile_library/trunk
27 added sync simplex FIFO unneback 4888d 04h /versatile_library/trunk
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4888d 06h /versatile_library/trunk
25 added sync FIFO unneback 4888d 19h /versatile_library/trunk
24 added vl_dff_ce_set unneback 4890d 03h /versatile_library/trunk
23 fixed port map error in async fifo 1r1w unneback 4890d 18h /versatile_library/trunk
22 added binary counters unneback 4890d 23h /versatile_library/trunk
21 reg -> wire in and or mux in logic unneback 4891d 19h /versatile_library/trunk
20 naming convention vl_ unneback 4893d 06h /versatile_library/trunk
19 naming convention vl_ unneback 4893d 06h /versatile_library/trunk
18 naming convention vl_ unneback 4893d 06h /versatile_library/trunk
17 unneback 4956d 19h /versatile_library/trunk

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