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[/] [versatile_library] - Rev 21

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21 reg -> wire in and or mux in logic unneback 4897d 19h /versatile_library
20 naming convention vl_ unneback 4899d 06h /versatile_library
19 naming convention vl_ unneback 4899d 06h /versatile_library
18 naming convention vl_ unneback 4899d 07h /versatile_library
17 unneback 4962d 20h /versatile_library
16 converting utility for ROM unneback 4963d 07h /versatile_library
15 added delay line unneback 4969d 04h /versatile_library
14 reg -> wire for various signals unneback 4969d 09h /versatile_library
13 cosmetic update unneback 4969d 10h /versatile_library
12 added wishbone comliant modules unneback 4970d 06h /versatile_library
11 async fifo simplex unneback 4970d 21h /versatile_library
10 added dff_ce_clear unneback 4972d 20h /versatile_library
9 added dff_ce_clear unneback 4972d 20h /versatile_library
8 added dff_ce_clear unneback 4972d 20h /versatile_library
7 mem update unneback 4972d 21h /versatile_library
6 added library files unneback 4985d 21h /versatile_library
5 memories added unneback 4985d 22h /versatile_library
4 added counters unneback 4990d 01h /versatile_library
3 various updates
counter added		 unneback 4992d 21h /versatile_library
2 initial check-in unneback 4993d 21h /versatile_library

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