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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 4885d 19h /
28 added sync simplex FIFO unneback 4886d 20h /
27 added sync simplex FIFO unneback 4886d 20h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4886d 21h /
25 added sync FIFO unneback 4887d 11h /
24 added vl_dff_ce_set unneback 4888d 18h /
23 fixed port map error in async fifo 1r1w unneback 4889d 09h /
22 added binary counters unneback 4889d 14h /
21 reg -> wire in and or mux in logic unneback 4890d 10h /
20 naming convention vl_ unneback 4891d 21h /
19 naming convention vl_ unneback 4891d 21h /
18 naming convention vl_ unneback 4891d 21h /
17 unneback 4955d 11h /
16 converting utility for ROM unneback 4955d 22h /
15 added delay line unneback 4961d 19h /
14 reg -> wire for various signals unneback 4962d 00h /
13 cosmetic update unneback 4962d 01h /
12 added wishbone comliant modules unneback 4962d 21h /
11 async fifo simplex unneback 4963d 12h /
10 added dff_ce_clear unneback 4965d 11h /
9 added dff_ce_clear unneback 4965d 11h /
8 added dff_ce_clear unneback 4965d 11h /
7 mem update unneback 4965d 12h /
6 added library files unneback 4978d 12h /
5 memories added unneback 4978d 13h /
4 added counters unneback 4982d 16h /
3 various updates
counter added
unneback 4985d 12h /
2 initial check-in unneback 4986d 12h /
1 The project and the structure was created root 4991d 16h /

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