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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 4859d 02h /
31 sync FIFO updated unneback 4878d 22h /
30 updated counter for level1 and level2 function unneback 4878d 22h /
29 updated counter for level1 and level2 function unneback 4878d 22h /
28 added sync simplex FIFO unneback 4879d 23h /
27 added sync simplex FIFO unneback 4879d 23h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4880d 01h /
25 added sync FIFO unneback 4880d 14h /
24 added vl_dff_ce_set unneback 4881d 22h /
23 fixed port map error in async fifo 1r1w unneback 4882d 12h /
22 added binary counters unneback 4882d 18h /
21 reg -> wire in and or mux in logic unneback 4883d 14h /
20 naming convention vl_ unneback 4885d 01h /
19 naming convention vl_ unneback 4885d 01h /
18 naming convention vl_ unneback 4885d 01h /
17 unneback 4948d 14h /
16 converting utility for ROM unneback 4949d 02h /
15 added delay line unneback 4954d 22h /
14 reg -> wire for various signals unneback 4955d 03h /
13 cosmetic update unneback 4955d 05h /

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