URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 46

Rev	Log message	Author	Age	Path
46	updated parity	unneback	4829d 07h	/
45	updated timing in io models	unneback	4831d 02h	/
44	added target independet IO functionns	unneback	4834d 01h	/
43	added logic for parity generation and check	unneback	4838d 05h	/
42	updated mux_andor	unneback	4842d 04h	/
41	typo in registers.v	unneback	4842d 06h	/
40	new build environment with custom.v added as a result file	unneback	4842d 06h	/
39	added simple port prio based wb arbiter	unneback	4843d 03h	/
38	updated andor mux	unneback	4843d 03h	/
37	corrected polynom with length 20	unneback	4849d 00h	/
36	added generic andor_mux	unneback	4850d 08h	/
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	4850d 19h	/
34	added vl_mux2_andor and vl_mux3_andor	unneback	4850d 19h	/
33	updated wb3wb3_bridge	unneback	4863d 21h	/
32	added vl_pll for ALTERA (cycloneIII)	unneback	4871d 07h	/
31	sync FIFO updated	unneback	4891d 03h	/
30	updated counter for level1 and level2 function	unneback	4891d 03h	/
29	updated counter for level1 and level2 function	unneback	4891d 03h	/
28	added sync simplex FIFO	unneback	4892d 04h	/
27	added sync simplex FIFO	unneback	4892d 04h	/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4892d 06h	/
25	added sync FIFO	unneback	4892d 19h	/
24	added vl_dff_ce_set	unneback	4894d 03h	/
23	fixed port map error in async fifo 1r1w	unneback	4894d 18h	/
22	added binary counters	unneback	4894d 23h	/
21	reg -> wire in and or mux in logic	unneback	4895d 19h	/
20	naming convention vl_	unneback	4897d 06h	/
19	naming convention vl_	unneback	4897d 06h	/
18	naming convention vl_	unneback	4897d 06h	/
17		unneback	4960d 19h	/