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Rev Log message Author Age Path
46 updated parity unneback 4118d 20h /
45 updated timing in io models unneback 4120d 14h /
44 added target independet IO functionns unneback 4123d 14h /
43 added logic for parity generation and check unneback 4127d 17h /
42 updated mux_andor unneback 4131d 17h /
41 typo in registers.v unneback 4131d 18h /
40 new build environment with custom.v added as a result file unneback 4131d 18h /
39 added simple port prio based wb arbiter unneback 4132d 15h /
38 updated andor mux unneback 4132d 15h /
37 corrected polynom with length 20 unneback 4138d 12h /
36 added generic andor_mux unneback 4139d 20h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4140d 07h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4140d 08h /
33 updated wb3wb3_bridge unneback 4153d 10h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4160d 19h /
31 sync FIFO updated unneback 4180d 15h /
30 updated counter for level1 and level2 function unneback 4180d 15h /
29 updated counter for level1 and level2 function unneback 4180d 15h /
28 added sync simplex FIFO unneback 4181d 17h /
27 added sync simplex FIFO unneback 4181d 17h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4181d 18h /
25 added sync FIFO unneback 4182d 07h /
24 added vl_dff_ce_set unneback 4183d 15h /
23 fixed port map error in async fifo 1r1w unneback 4184d 06h /
22 added binary counters unneback 4184d 11h /
21 reg -> wire in and or mux in logic unneback 4185d 07h /
20 naming convention vl_ unneback 4186d 18h /
19 naming convention vl_ unneback 4186d 18h /
18 naming convention vl_ unneback 4186d 18h /
17 unneback 4250d 08h /

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