URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [syn] - Rev 93

Rev	Log message	Author	Age	Path
93		unneback	5042d 17h	/versatile_mem_ctrl/tags/Rev1/syn
86		mikaeljf	5095d 00h	/versatile_mem_ctrl/trunk/syn
84		mikaeljf	5099d 23h	/versatile_mem_ctrl/trunk/syn
83		mikaeljf	5100d 19h	/versatile_mem_ctrl/trunk/syn
81		mikaeljf	5101d 20h	/versatile_mem_ctrl/trunk/syn
75		mikaeljf	5154d 18h	/versatile_mem_ctrl/trunk/syn
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5188d 17h	/versatile_mem_ctrl/trunk/syn
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5208d 12h	/versatile_mem_ctrl/trunk/syn
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5212d 15h	/versatile_mem_ctrl/trunk/syn
20	Minor update of sdc-file.	mikaeljf	5214d 16h	/versatile_mem_ctrl/trunk/syn
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5220d 21h	/versatile_mem_ctrl/trunk/syn
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5225d 17h	/versatile_mem_ctrl/trunk/syn
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5315d 23h	/versatile_mem_ctrl/trunk/syn