URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2] - Rev 109

Rev	Log message	Author	Age	Path
82		mikaeljf	5093d 09h	/versatile_mem_ctrl/tags/Rev2
81		mikaeljf	5094d 05h	/versatile_mem_ctrl/tags/Rev2
80		mikaeljf	5094d 06h	/versatile_mem_ctrl/tags/Rev2
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5131d 20h	/versatile_mem_ctrl/tags/Rev2
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5134d 03h	/versatile_mem_ctrl/tags/Rev2
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5142d 02h	/versatile_mem_ctrl/tags/Rev2
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5147d 03h	/versatile_mem_ctrl/tags/Rev2
75		mikaeljf	5147d 04h	/versatile_mem_ctrl/tags/Rev2
74	Minor update of rtl Makefile.	mikaeljf	5151d 03h	/versatile_mem_ctrl/tags/Rev2
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5151d 04h	/versatile_mem_ctrl/tags/Rev2