OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 added texinfo User guide and updated fsm unneback 4822d 00h /versatile_mem_ctrl/trunk/bench/
99 updated stimuli with automatic check unneback 4860d 08h /versatile_mem_ctrl/trunk/bench/
94 new TB unneback 5007d 10h /versatile_mem_ctrl/trunk/bench/
82 mikaeljf 5076d 13h /versatile_mem_ctrl/trunk/bench/
80 mikaeljf 5077d 11h /versatile_mem_ctrl/trunk/bench/
75 mikaeljf 5130d 08h /versatile_mem_ctrl/trunk/bench/
74 Minor update of rtl Makefile. mikaeljf 5134d 07h /versatile_mem_ctrl/trunk/bench/
70 mikaeljf 5137d 16h /versatile_mem_ctrl/trunk/bench/
69 mikaeljf 5138d 12h /versatile_mem_ctrl/trunk/bench/
35 work for limited test case unneback 5159d 07h /versatile_mem_ctrl/trunk/bench/
33 work for limited test case, no cke inhibit for fifo empty unneback 5159d 10h /versatile_mem_ctrl/trunk/bench/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5162d 14h /versatile_mem_ctrl/trunk/bench/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5168d 07h /versatile_mem_ctrl/trunk/bench/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5168d 09h /versatile_mem_ctrl/trunk/bench/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5197d 08h /versatile_mem_ctrl/trunk/bench/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5200d 07h /versatile_mem_ctrl/trunk/bench/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5201d 08h /versatile_mem_ctrl/trunk/bench/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5291d 10h /versatile_mem_ctrl/trunk/bench/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5291d 13h /versatile_mem_ctrl/trunk/bench/
12 Minor update of whishbone FSMs in TB mikaeljf 5301d 14h /versatile_mem_ctrl/trunk/bench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.