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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 111

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Rev Log message Author Age Path
111 major update unneback 4662d 21h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
98 updates unneback 4978d 00h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
97 updated tb and sdram16 unneback 4978d 13h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
95 new files unneback 5013d 14h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
74 Minor update of rtl Makefile. mikaeljf 5148d 19h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5148d 20h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5148d 21h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
69 mikaeljf 5153d 00h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5155d 15h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5159d 23h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5166d 17h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5166d 18h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
42 added pipeline stage for egress FIFO readot unneback 5169d 11h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
39 updated FIFO and SDR 16 unneback 5170d 13h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
37 unneback 5173d 11h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
35 work for limited test case unneback 5173d 19h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
33 work for limited test case, no cke inhibit for fifo empty unneback 5173d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5178d 19h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5182d 21h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
25 unneback 5188d 14h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile

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