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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 97

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97 updated tb and sdram16 unneback 4980d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
95 new files unneback 5015d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
74 Minor update of rtl Makefile. mikaeljf 5151d 03h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5151d 04h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5151d 06h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
69 mikaeljf 5155d 09h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5157d 23h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5162d 07h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5169d 01h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5169d 03h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
42 added pipeline stage for egress FIFO readot unneback 5171d 20h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
39 updated FIFO and SDR 16 unneback 5172d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
37 unneback 5175d 20h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
35 work for limited test case unneback 5176d 04h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
33 work for limited test case, no cke inhibit for fifo empty unneback 5176d 06h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5181d 03h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5185d 05h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
25 unneback 5190d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5191d 10h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5200d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile

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