URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

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Rev	Log message	Author	Age	Path
56	Removed 'or negedge arst' from sluint/luint sensitivity list	rherveille	7627d 02h	/
55	Initial release.	rherveille	7684d 02h	/
54	Added DVI tests	rherveille	7684d 02h	/
53	Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. Blocks are located more logically now. Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.	rherveille	7684d 07h	/
52	Numerous updates and added checks	rherveille	7684d 07h	/
51	Forgot to change document revision number	rherveille	7732d 02h	/
50	Forgot to change document revision	rherveille	7732d 02h	/
49	Added WISHBONE revB.3 signals	rherveille	7732d 03h	/
48	WISHBONE revB.3 signals added	rherveille	7732d 03h	/
47	Added wb_b3_check Removed ud_cnt, ro_cnt	rherveille	7732d 23h	/
46	Added WISHBONE revB.3 sanity checks	rherveille	7732d 23h	/
45	Changed timing generator; made it smaller and easier.	rherveille	7733d 04h	/
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7733d 04h	/
43	Added WISHBONE revB.3 Registered Feedback Cycles support	rherveille	7733d 19h	/
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8066d 05h	/
41	specs version 1.1	rherveille	8066d 05h	/
40	no message	rherveille	8066d 05h	/
39	Changed video timing generator. Changed wishbone master vertical gate count code. Fixed a potential bug in the wishbone slave (cursor color register readout).	rherveille	8066d 07h	/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8066d 07h	/
37	Fixed a potential reset bug in the hint & vint generation.	rherveille	8081d 10h	/

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Subversion Repositories vga_lcd

[/] - Rev 56

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