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Rev Log message Author Age Path
62 New directory structure. root 5533d 21h /
61 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7528d 18h /
60 all WB outputs are registered, but just when we dont use cursors markom 7528d 18h /
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7561d 00h /
58 Enabled Fifo Underrun test rherveille 7561d 00h /
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7581d 20h /
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7610d 16h /
55 Initial release. rherveille 7667d 17h /
54 Added DVI tests rherveille 7667d 17h /
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7667d 22h /
52 Numerous updates and added checks rherveille 7667d 22h /
51 Forgot to change document revision number rherveille 7715d 16h /
50 Forgot to change document revision rherveille 7715d 16h /
49 Added WISHBONE revB.3 signals rherveille 7715d 17h /
48 WISHBONE revB.3 signals added rherveille 7715d 17h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7716d 14h /
46 Added WISHBONE revB.3 sanity checks rherveille 7716d 14h /
45 Changed timing generator; made it smaller and easier. rherveille 7716d 19h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7716d 19h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7717d 10h /

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